1. Field of the Invention
The present invention relates to integrated circuits and, in particular, to a high density, parallel refresh cell for a dynamic random access memory. A memory array utilizing parallel refresh cells in accordance with the present invention can be refreshed in a single access or refresh cycle. .
2. Discussion of the Prior Art
If no read or write cycles are performed on a cell of a dynamic memory within a period of time, then the stored voltage levels of the cell begin to decay and must be "refreshed".
FIG. 1 shows a 4-transistor parallel refresh cell for a random access memory (RAM). As shown in FIG. 1, field effect transistors (FETs) 10 and 12 are connected sequentially between a supply voltage V.sub.CC and a column line of a RAM. An MOS capacitor 14 is connected between a pump input and the gate of transistor 10. A third field effect transistor 16 has control a signal PC applied to its source while its drain is connected to the gate of transistor 10. The gate of transistor 12 is connected to receive a row (or word) line signal of the RAM.
During refresh, signal PC stays at the V.sub.CC level and the pump signal toggles between V.sub.SS and V.sub.CC. During a read cycle, the signal PC and the PUMP signal remain at V.sub.CC and the row line signal goes high. During a write cycle, signal PC and the pump signal go to ground while the row line signal goes high.
Assume that a "1" has been written to node S in FIG. 1. As stated above, if no read or write cycles have been performed during an approximately 4 msec period, then the voltage levels at nodes G and S will decay due to leakage. Therefore, a "refresh" must be performed.
On receiving a refresh signal, control signal PC stays at V.sub.CC level and PUMP will go to ground. If node S is at a voltage.gtoreq.2V.sub.T, then at least 1V.sub.T will pass from PC to node G through transistor 16. Therefore, MOS capacitor 14 will be on. Where V.sub.T is the treshold voltage, then PUMP goes to V.sub.CC, boosting node G to a voltage lead of at least V.sub.CC +1V.sub.T. This opens transistor 10 and restores the voltage level of node S to V.sub.CC.
In the Read Mode, PUMP temporarily goes low during propagation of a new address through the row and column decoders. The PC signal stays high. If node S is at a voltage greater than or equal to 2V.sub.T, then node G will be at least at the 1V.sub.T level. Then PUMP goes to V.sub.DD and capacitively pulses node G to at least V.sub.DD +V.sub.T level, connecting node S to the V.sub.CC power supply through transistor 10. This sustains a "1" at node S.
In the case where node S is at the OV level, transistor 16 is closed and no charge penetrates to node G from PC. Capacitor 14 is also off and has no effect on node G. Therefore, the "0" at node S remains unchanged. Since the PUMP and PC signals are connected to each individual cell within the memory, all cells are refreshed in parallel during the Read Cycle.
The conventional refresh cell configuration described above in conjunction with FIG. 1 suffers from two major disadvantages. First, it requires a relatively large number of devices for the function provided. Second, it requires a complicated control scheme.